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19-0486; Rev 3; 12/05
+5V Microprocessor Supervisory Circuits
General Description
The MAX817/MAX818/MAX819 microprocessor (P) supervisory circuits simplify power-supply monitoring, battery control, and chip-enable gating in P systems by reducing the number of components required. These devices are designed for use in +5V-powered systems. Low supply current (11A typical) and small package size make these devices ideal for portable applications. The MAX817/MAX818/MAX819 are specifically designed to ignore fast transients on VCC. Other supervisory functions include active-low reset, backupbattery switchover, watchdog input, battery freshness seal, and chip-enable gating. The Selector Guide below lists the specific functions available from each device. These devices offer two pretrimmed reset threshold voltages for 5% or 10% power supplies: 4.65V for the L versions and 4.40V for the M versions. The MAX817/ MAX818/MAX819 are available in space-saving MAX packages, as well as 8-pin DIP/SO.
____________________________Features
Precision Supply-Voltage Monitor: 4.65V (MAX81_L) 4.40V (MAX81_M) 11A Quiescent Supply Current 200ms Reset Time Delay Watchdog Timer with 1.6sec Timeout (MAX817/MAX818) Battery-Backup Power Switching; Battery Voltage Can Exceed VCC Battery Freshness Seal On-Board, 3ns Gating of Chip-Enable Signals (MAX818) Uncommitted Voltage Monitor for Power-Fail or Low-Battery Warning (MAX817/MAX819) Manual Reset Input (MAX819)
MAX817L/M, MAX818L/M, MAX819L/M*
_____________________Selector Guide
FEATURE Active-Low Reset Backup-Battery Switchover Power-Fail Comparator Watchdog Input Battery Freshness Seal Manual Reset Input Chip-Enable Gating Pin-Package MAX817 L/M -- -- MAX818 L/M -- -- MAX819 L/M -- --
______________Ordering Information
PART MAX817_CPA MAX817_CSA MAX817_CUA TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 8 Plastic DIP 8 SO 8 MAX
Ordering Information continued on last page. These parts offer a choice of reset threshold voltage. From the table below, select the suffix corresponding to the desired threshold and insert it into the blank to complete the part number. Devices are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. SUFFIX L M RESET THRESHOLD (V) 4.65 4.40
8-DIP/SO/ 8-DIP/SO/ 8-DIP/SO/ MAX MAX MAX -- MAX703/ MAX704
Low-Power, PinMAX690A/ Compatible Upgrades for: MAX692A
_________________Pin Configurations ________________________Applications
Battery-Powered Computers and Controllers Embedded Controllers Intelligent Instruments Critical P Monitoring Portable Equipment
TOP VIEW
OUT 1 VCC 2 GND 3 PFI 4
8
BATT RESET WDI PFO
MAX817
7 6 5
Typical Operating Circuit appears at end of data sheet. *P
DIP/SO/MAX Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
ABSOLUTE MAXIMUM RATINGS
Input Voltage VCC, BATT ..........................................................-0.3V to +6.0V All Other Pins (Note 1).............................-0.3V to (VCC + 0.3V) Input Current VCC Peak ..............................................................................1A VCC Continuous .............................................................250mA BATT Peak .....................................................................250mA BATT Continuous .............................................................50mA GND .................................................................................25mA Output Current OUT................................................................................250mA All Other Outputs .............................................................25mA OUT Short-Circuit Duration.................................................10sec Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 9.09mW/C above +70C) .............727mW SO (derate 5.88mW/C above +70C) ..........................471mW MAX (derate 4.10mW/C above +70C) .....................330mW Operating Temperature Ranges MAX81_ _C_A ......................................................0C to +70C MAX81_ _E_A ...................................................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Note 1: The input voltage limits on PFI and WDI may be exceeded (up to 12V VIN) if the current into these pins is limited to less than 10mA.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Operating Voltage Range, VCC, VBATT (Note 2) Supply Current (excluding IOUT) Supply Current in BatteryBackup Mode (excluding IOUT) ISUPPLY As applicable; CE IN = 0V, WDI and MR unconnected VCC = 0V MAX81_ _C MAX81_ _E TA = +25C TA = TMIN to TMAX TA = +25C BATT Standby Current (Note 3) BATT Leakage Current, Freshness Seal Enabled 5.5V > VCC > (VBATT + 0.2V) TA = TMIN to TMAX -0.10 -1.00 SYMBOL CONDITIONS MIN 0 11 11 0.05 TYP MAX 5.5 45 60 1.0 5.0 0.02 0.02 1 VCC 0.05 VCC 0.5 VCC 0.025 VCC 0.25 5 100 IOUT = 250A, VCC < (VBATT - 0.2V) VCC < VRST Power-up Power-down VBATT - VBATT 0.1 0.02 20 -20 40 10 A A UNITS V A
VCC = 0V, VOUT = 0V IOUT = 5mA
A
VOUT Output IOUT = 50mA VCC to OUT On-Resistance BATT to OUT On-Resistance VOUT in Battery-Backup Mode Battery Switch Threshold (VCC - VBATT) Battery Switchover Hysteresis
V
V mV mV
2
_______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL MAX81_L MAX81_M CONDITIONS MIN 4.50 4.25 140 VCC > VRST(MAX), ISOURCE = 800A VCC < VRST(MIN), ISINK = 3.2mA RESET Output Voltage VOL MAX81_ _C, VCC = 1V, VCC falling, VBATT = 0V, ISINK = 50A MAX81_ _E, VCC = 1.2V, VCC falling, VBATT = 0V, ISINK = 100A VCC to RESET Delay Watchdog Timeout Period WDI Pulse Width WDI Input Threshold (Note 4) WDI Input Current (Note 5) tWD tWDI VIL VIH VIL = 0.4V, VIH = 0.8VCC VCC = 5V WDI = VCC, time average WDI = GND, time average VPFT IPFI VOL VOH VPFI < 1.20V, ISINK = 3.2mA, VCC > 4.50V VPFI > 1.30V, ISOURCE = 40A, VCC > 4.5V V P FO = 0V VIL VIH 1 100 120 45 63 85 0.8 2.0 VCC - 1.5 250 500 -20 1.20 -25 From VRST, VCC falling at 10V/ms 1.00 50 0.8 3.5 120 -15 1.25 4 0.01 25 0.4 1.30 160 100 1.60 2.25 VCC - 1.5 0.4 0.3 0.3 s sec ns V A V TYP 4.65 4.40 25 tRP VOH 200 280 MAX 4.75 4.50 UNITS RESET AND WATCHDOG TIMER Reset Threshold Reset Threshold Hysteresis Reset Timeout Period VRST V mV ms
MAX817L/M, MAX818L/M, MAX819L/M*
POWER-FAIL COMPARATOR (MAX817/MAX819 only) PFI Input Threshold PFI Input Hysteresis PFI Input Current PFO Output Voltage PFO Short-Circuit Current MANUAL RESET INPUT (MAX819 only) MR Input Threshold MR Pulse Width MR Pulse that Would Not Cause a Reset MR to Reset Delay MR Pull-Up Resistance V s ns ns k V mV nA V A
_______________________________________________________________________________________
3
+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CE IN Leakage Current CE IN to CE OUT Resistance (Note 6) CE OUT Short-Circuit Current (Reset Active) CE IN to CE OUT Propagation Delay (Note 7) CE OUT Output CE OUT Input Threshold RESET to CE OUT Delay Note 2: Note 3: Note 4: Note 5: VOH VIH VIL SYMBOL Disable mode Enable mode Disable mode, CE OUT = 0V 50 source impedance driver, CLOAD = 50pF IOUT = -100A, VCC = 0V IOUT = -1A, VCC = 0V, VBATT = 2.8V VCC = 5V Power-down VCC - 1V 2.7 0.8 3.5 15 0.1 CONDITIONS MIN TYP 0.005 40 0.75 3 MAX 1 150 2.0 8 UNITS A mA ns V V s CHIP-ENABLE GATING (MAX818 only)
Either VCC or VBATT can go to 0V if the other is greater than 2.0V. "-" = battery-charging current, "+" = battery-discharging current. WDI is internally serviced within the watchdog timeout period if WDI is left unconnected. WDI input is designed to be driven by a three-stated output device. To float WDI, the "high-impedance mode" of the output device must have a maximum leakage current of 10A and a maximum output capacitance of 200pF. The output device must also be able to source and sink at least 200A when active. Note 6: The chip-enable resistance is tested with VCC = +4.75V for the MAX818L and VCC = +4.5V for the MAX818M. V C E IN = V C E OUT = VCC/2. Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
4
_______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
__________________________________________Typical Operating Characteristics
(VCC = +5V, VBATT = 3.0V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (NO LOAD)
MAX817/18/19-01
BATTERY SUPPLY CURRENT (BACKUP MODE) vs. TEMPERATURE
CE IN TO CE OUT ON-RESISTANCE () 140 120 100 80 60 40 20 0 VBATT = 2.8V VBATT = 2.0V VCC = 0V VBATT = 5.0V
MAX817/18/19-02
CE IN TO CE OUT ON-RESISTANCE vs. TEMPERATURE
90 80 70 60 50 40 30 20 10 0 -40 -20 0 20 40 60 80 100 VCE IN = 3V VCE IN = 2V
MAX817/18/19-03
16
160 BATTERY SUPPLY CURRENT (nA)
100 VCE IN = 4V
SUPPLY CURRENT (A)
14
12
10
8 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
-40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
BATT TO OUT ON-RESISTANCE vs. TEMPERATURE
MAX817/18/19-04
VCC TO OUT ON-RESISTANCE vs. TEMPERATURE
MAX817/18/19-05
RESET TIMEOUT PERIOD vs. TEMPERATURE
MAX817/18/19-06
300 BATT TO OUT ON-RESISTANCE () 250 200 150 100 50 0 -40
VCC = 0V
7 VCC TO OUT ON-RESISTANCE ()
220 RESET TIMEOUT PERIOD (ms)
VBATT = 2.0V
6
210
VBATT = 2.8V VBATT = 5.0V
5
200
4
190
3 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C)
180 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
VCC TO RESET PROPAGATION DELAY vs. TEMPERATURE
MAX817/18/19-07
WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
WATCHDOG TIMEOUT PERIOD (sec)
MAX817/18/19-08
BATTERY FRESHNESS SEAL LEAKAGE CURRENT vs. TEMPERATURE
MAX817/18/19-09
VCC TO RESET PROPAGATION DELAY (ms)
500 VCC FALLING AT: 0.25V/ms 400
1.70
20
LEAKAGE CURRENT (nA)
1.65
15
300 1V/ms 200 10V/ms 100
1.60
10
1.55
5
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
1.50 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
_______________________________________________________________________________________
5
+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
____________________________Typical Operating Characteristics (continued)
(VCC = +5V, VBATT = 3.0V, TA = +25C, unless otherwise noted.)
RESET THRESHOLD vs. TEMPERATURE
MAX817/18/19-10
MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE
MAX817/18/19-11
BATTERY SUPPLY CURRENT vs. SUPPLY VOLTAGE
7 6 5 4 3 2 1 0
MAX817/18/19-12
4.7 MAX81_L 4.6
1600 MAXIMUM TRANSIENT DURATION (s) 1400 1200 1000 800 600 400 200 0 RESET OCCURS ABOVE CURVE
8 BATTERY SUPPLY CURRENT (A)
RESET THRESHOLD (V)
4.5
4.4
MAX81_M
4.3 -40
-20
0
20
40
60
80
1
10
100
1000
10,000
0
1
2
3 VCC (V)
4
5
6
TEMPERATURE (C)
RESET COMPARATOR OVERDRIVE, VTH-VCC (mV)
CE IN TO CE OUT PROPAGATION DELAY vs. TEMPERATURE
CE IN TO CE OUT PROPAGATION DELAY (ns)
MAX817/18/19-13
MAX817/MAX819 PFI THRESHOLD vs. TEMPERATURE
MAX817/18/19-14
MAX817/MAX819 PFI TO PFO PROPAGATION DELAY vs. TEMPERATURE
MAX817/18/19-15
7 6 5 4 3 tPD+ 2 1 0 -40 -20 0 20 40 60 80 tPD-
1.254 1.252 1.250 1.248 1.246 1.244 1.242 1.240
33
PROPAGATION DELAY (s)
32
THRESHOLD (V)
31
30
29
28 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C)
100
TEMPERATURE (C)
6
_______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
______________________________________________________________Pin Description
PIN NAME MAX817 1 2 3 4 MAX818 1 2 3 -- MAX819 1 2 3 4 OUT VCC GND PFI Supply Output for CMOS RAM. When VCC rises above the reset threshold or above VBATT, OUT is connected to VCC through an internal P-channel MOSFET switch. When VCC falls below VBATT, BATT connects to OUT. Input Supply Voltage, +5V input. Ground. 0V reference for all signals. Power-Fail Comparator Input. When VPFI is below VPFT or when VCC is below VBATT, PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator section). Connect to ground if unused. Chip-Enable Input. The input to the chip-enable gating circuit. Connect to ground if unused. Power-Fail Comparator Output. When PFI is less than VPFT or when VCC is below VBATT, PFO goes low; otherwise PFO remains high. PFO is also used to enable the battery freshness seal (see Battery Freshness Seal and Power-Fail Comparator sections). Chip-Enable Output. CE OUT goes low only if CE IN is low while reset is not asserted. If CE IN is low when reset is asserted, CE OUT will remain low for 15s or until CE IN goes high, whichever occurs first. CE OUT is pulled up to OUT in battery-backup mode. CE OUT is also used to enable the battery freshness seal (see Battery Freshness Seal section). Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and a reset is triggered. If WDI is left unconnected or is connected to a high-impedance three-state buffer, the watchdog feature is disabled. The internal watchdog timer clears whenever reset is asserted, WDI is three-stated, or WDI sees a rising or falling edge. The WDI input is designed to be driven by a three-statedoutput device with a maximum high-impedance leakage current of 10A and a maximum output capacitance of 200pF. The output device must also be capable of sinking and sourcing 200A when active. Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted for as long as MR is held low and for 200ms after MR returns high. The activelow input has an internal 63k pull-up resistor. It can be driven from a TTL- or CMOS-logic line or shorted to ground with a switch. Leave open, or connect to VCC if unused. Active-Low Reset Output. Pulses low for 200ms when triggered and remains low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for 200ms after VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes low to high. Backup-Battery Input. When VCC falls below VBATT, OUT switches from VCC to BATT. When VCC rises above VBATT, OUT reconnects to VCC. FUNCTION
MAX817L/M, MAX818L/M, MAX819L/M*
--
4
--
CE IN
5
--
5
PFO
--
5
--
CE OUT
6
6
--
WDI
--
--
6
MR
7
7
7
RESET
8
8
8
BATT
_______________________________________________________________________________________
7
+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
BATT
BATTERY SWITCHOVER CIRCUITRY
OUT
VCC
MAX817 MAX818 MAX819
RESET GENERATOR
RESET
1.25V THIS PIN FOR MAX819 ONLY.
MR WATCHDOG TIMER BATTERY FRESHNESS SEAL CIRCUITRY
WDI THIS SECTION FOR MAX817/ MAX818 ONLY.
THIS SECTION PFI FOR MAX817/ MAX819 ONLY.
PFO
1.25V
CHIP-ENABLE OUTPUT CONTROL
THIS SECTION FOR MAX818 ONLY. CE IN CE OUT
GND
Figure 1. Functional Diagram 8 _______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
_______________Detailed Description
General Timing Characteristics
Designed for 5V systems, the MAX817/MAX818/ MAX819 provide a number of microprocessor (P) supervisory functions (see the Selector Guide on the first page). Figure 2 shows the typical timing relationships of the various outputs during power-up and power-down with typical VCC rise and fall times. During the reset timeout period (tRP ), MR's state is ignored if the battery freshness seal is enabled. MR has an internal 63k pull-up resistor, so it can be left open if not used. This input can be driven with TTL/CMOSlogic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1F capacitor from MR to GND to provide additional noise immunity. Note that MR must be high or open to enable the battery freshness seal. Once the battery freshness seal is enabled its operation is unaffected by MR.
MAX817L/M, MAX818L/M, MAX819L/M*
RESET Output
A P's reset input starts the P in a known state. The MAX817/MAX818/MAX819 P supervisory circuits assert a reset to prevent code-execution errors during power-up, power-down, and brownout conditions. RESET is guaranteed to be a logic low for 0V < VCC < VRST if VBATT is greater than 1V. Without a backup battery (V BATT = GND) RESET is guaranteed valid for VCC 1V. Once VCC exceeds the reset threshold an internal timer keeps RESET low for the reset timeout period, t RP . After this interval RESET returns high (Figure 2). If a brownout condition occurs (VCC drops below the reset threshold), RESET goes low. Each time RESET is asserted it stays low for at least the reset timeout period. Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. RESET both sources and sinks current.
Battery Freshness Seal
The MAX817/MAX818/MAX819 battery freshness seal disconnects the backup battery from internal circuitry and OUT until it is needed. This allows an OEM to ensure that the backup battery connected to BATT will be fresh when the final product is put to use. To enable the freshness seal on the MAX817 and MAX819: 1) Connect a battery to BATT. 2) Ground PFO. 3) Bring V CC above the reset threshold and hold it there until reset is deasserted following the reset timeout period. 4) Bring VCC down again (Figure 3). Use the same procedure for the MAX818, but ground CE OUT instead of PFO. Once the battery freshness seal is enabled (disconnecting the backup battery from internal circuitry and anything connected to OUT), it remains enabled until VCC is brought above VRST.
Manual Reset Input (MAX819)
Many P-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. On the MAX819, a logic low on MR asserts reset. Reset remains asserted while MR is low, and for tRP (200ms) after it returns high.
VBATT VRST VCC VOUT VRESET VPFO* VCE OUT** VBATT CE OUT FOLLOWS CE IN *MAX817/MAX819 ONLY. ** MAX818 ONLY. VBATT tRP PFO FOLLOWS PFI RESET TO CE OUT DELAY** VRST VBATT
VRST
VRST
VCC tRP CE OUT STATE LATCHED AT 1/2 tRP AND 3/4 tRP, FRESHNESS SEAL ENABLED PFO STATE LATCHED AT 1/2 tRP AND 3/4 tRP, FRESHNESS SEAL ENABLED
RESET
CE OUT (MAX818) (EXTERNALLY HELD AT 0V) PFO (MAX817/MAX819) (EXTERNALLY HELD AT 0V)
Figure 2. Power-Up and Power-Down Timing
Figure 3. Battery Freshness Seal Timing 9
_______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
On the MAX819, MR must be high or open to enable the battery freshness seal. Once the battery freshness seal is enabled its operation is unaffected by MR.
Watchdog Input (MAX817/MAX818)
In the MAX817/MAX818, the watchdog circuit monitors the P's activity. If the P does not toggle the watchdog input (WDI) within tWD (1.6sec), reset asserts. The internal 1.6sec timer is cleared by either a reset pulse or by toggling WDI, which can detect pulses as short as 50ns. The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (Figure 4). To disable the watchdog function, leave WDI unconnected or three-state the driver connected to WDI. The watchdog input is internally driven low during the first 7/8 of the watchdog timeout period, then momentarily pulses high, resetting the watchdog counter. When WDI is left open-circuited, this internal driver clears the 1.6sec timer every 1.4sec. When WDI is three-stated or left unconnected, the maximum allowable leakage current is 10A and the maximum allowable load capacitance is 200pF.
VCC tRP RESET tWD
WDI
Figure 4. Watchdog Timing
MAX817 MAX818
RESET GENERATOR
BATTERY SWITCHOVER CIRCUITRY
BATTERY FRESHNESS SEAL CIRCUITRY OUT
Chip-Enable Gating (MAX818)
Internal gating of the chip-enable (CE) signal prevents erroneous data from corrupting CMOS RAM in the event of an undervoltage condition. The MAX818 uses a series transmission gate from CE IN to CE OUT (Figure 5). During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short CE propagation delay from CE IN to CE OUT enables the MAX818 to be used with most Ps. If CE IN is low when reset asserts, CE OUT remains low for typically 15s to permit the current write cycle to complete.
CHIP-ENABLE OUTPUT CONTROL P CE IN N
CE OUT
Figure 5. Chip-Enable Transmission Gate
Chip-Enable Input (MAX818)
The CE transmission gate is disabled and CE IN is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC passes the reset threshold, the CE transmission gate disables and CE IN immediately becomes high impedance if the voltage at CE IN is high. If CE IN is low when reset asserts, the CE transmission gate will disable 15s after reset asserts (Figure 6). This permits the current write cycle to complete during power-down.
VRST VCC VRST VRST VRST
VCE OUT
VBATT tRP
VBATT tRP
15s
VRESET VCE IN
Figure 6. Chip-Enable Timing 10 ______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
Any time a reset is generated, the CE transmission gate remains disabled and CE IN remains high impedance (regardless of CE IN activity) for the reset timeout period. When the CE transmission gate is enabled, the impedance of CE IN appears as a 40 resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on VCC, the source impedance of the drive connected to CE IN, and the loading on CE OUT (see Typical Operating Characteristics). The CE propagation delay is production tested from the 50% point on CE IN to the 50% point on CE OUT using a 50 driver and a 50pF load capacitance (Figure 7). For minimum propagation delay, minimize the capacitive load at CE OUT and use a low-output-impedance driver.
Power-Fail Comparator (MAX817/MAX819)
The MAX817/MAX819 PFI input is compared to an internal reference. If PFI is less than the power-fail threshold (VPFT), PFO goes low. The power-fail comparator is intended for use as an undervoltage detector to signal a failing power supply (Figure 8). However, the comparator does not need to be dedicated to this function because it is completely separate from the rest of the circuitry. The power-fail comparator turns off and PFO goes low when VCC falls below VBATT. During the reset timeout period (tRP), PFO is forced high, regardless of the state of VPFI (see Battery Freshness Seal section). If the comparator is unused, connect PFI to ground and leave PFO unconnected. PFO can be connected to MR on the MAX819 so that a low voltage on PFI will generate a reset (Figure 9). In this configuration, when the monitored voltage causes PFI to fall below VPFT, PFO pulls MR low, causing a reset to be asserted. Reset remains asserted as long as PFO holds MR low, and for tRP (200ms) after PFO pulls MR high when the monitored supply is above the programmed threshold. When PFO is connected to MR, it is not possible to enable the battery freshness seal. Enabling the battery freshness seal requires MR to be high or open. Once the battery freshness seal is enabled, it is no longer affected by PFO's connection to MR.
MAX817L/M, MAX818L/M, MAX819L/M*
Chip-Enable Output (MAX818)
When the CE transmission gate is enabled, the impedance of CE OUT is equivalent to a 40 resistor in series with the source driving CE IN. In the disabled mode, the transmission gate is off and an active pull-up connects CE OUT to OUT (Figure 5). This pull-up turns off when the transmission gate is enabled.
+5V VCC BATT
VIN
+5V REGULATOR
POWER-FAIL-WARNING TRIP VOLTAGE R1 + R2 VWARN = 1.25 R2
(
)
MAX818
VCC
CE IN 50 50 GND
CE OUT
R1 PFI 50pF CL* R2
MAX817 MAX819
RESET
RESET
PFO
NMI
P
1.25V * CL INCLUDES LOAD CAPACITANCE, STRAY CAPACITANCE, AND SCOPE-PROBE CAPACITANCE.
Figure 7. CE Propagation Delay Test Circuit
Figure 8. Using the Power-Fail Comparator to Generate a Power-Fail Warning 11
______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
Backup-Battery Switchover
In a brownout or power failure, it may be necessary to preserve the contents of RAM. With a backup battery installed at BATT, the MAX817/MAX818/MAX819 automatically switch RAM to backup power when VCC falls. These devices require two conditions before switching to battery-backup mode: 1) VCC must be below the reset threshold, and 2) V CC must be below V BATT . Table 1 lists the status of the inputs and outputs in battery-backup mode. As long as VCC exceeds the reset threshold, OUT connects to VCC through a 5 PMOS power switch. Once V CC falls below the reset threshold, V CC or V BATT (whichever is higher) switches to OUT. When VCC falls below VRST and VBATT, BATT switches to OUT through an 80 switch. When VCC exceeds the reset threshold, it is connected to the substrate, regardless of the voltage applied to BATT (Figure 10). During this time, the diode (D1) between BATT and the substrate will conduct current from BATT to VCC if VBATT is 0.6V greater than VCC. When BATT connects to OUT, backup mode is activated and the internal circuitry is powered from the battery (Table 1). When VCC is just below VBATT, the current draw from BATT is typically 6A. When VCC drops to more than 1V below VBATT, the internal switchover comparator shuts off and the supply current falls to less than 1A.
__________Applications Information
The MAX817/MAX818/MAX819 are protected for typical short-circuit conditions of 10sec or less. Shorting OUT to ground for longer than 10sec destroys the device. Decouple VCC, OUT, and BATT to ground by placing 0.1F capacitors as close to the device as possible.
Table 1. Input and Output Status in Battery-Backup Mode
SIGNAL VCC VOUT STATUS Disconnected from VOUT. Connected to VBATT through an internal 80 PMOS switch. Connected to VOUT. Current drawn from the battery is less than 1A, as long as VCC < VBATT - 0.2V. Logic low Watchdog timer is disabled. Logic high. The open-circuit voltage is equal to VOUT. High impedance
MAX817 MAX818 MAX819 D3 BATT VCC
VBATT V R ESET VWDI V C E OUT V C E IN
SW1
SW2
D1
D2
SW3
SW4
SUBSTRATE
OUT V1 ADDITIONAL SUPPLY RESET VOLTAGE R1 + R2 V2 (RESET) = 1.25 R2
V2
VCC
(
)
CONDITION VCC > Reset Threshold
SW1/SW2 Open Open Closed
SW3/SW4 Closed Closed Open
R1 PFI R2
MAX819
RESET MR PFO P RESET
VCC < Reset Threshold and VCC > VBATT VCC < Reset Threshold and VCC < VBATT
RESET THRESHOLD = 4.65V IN MAX81_L RESET THRESHOLD = 4.4V IN MAX81_M
Figure 9. Monitoring an Additional Supply by Connecting PFO to MR. 12
Figure 10. Backup-Battery-Switchover Block Diagram
______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
Watchdog Input Current
The MAX817/MAX818 WDI inputs are internally driven through a buffer and series resistor from the watchdog counter (Figure 1). When WDI is left unconnected, the watchdog timer is serviced within the watchdog timeout period by a low-high-low pulse from the counter chain. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog timeout period, pulsing it low-high-low once within 7/8 of the watchdog timeout period to reset the watchdog timer. If instead WDI is externally driven high for the majority of the timeout period, up to 150A can flow into WDI. VCC, the SuperCap on BATT discharges through VCC until VBATT reaches the reset threshold. Battery-backup mode is then initiated and the current through V CC goes to zero.
MAX817L/M, MAX818L/M, MAX819L/M*
Operation Without a Backup Power Source
The MAX817/MAX818/MAX819 were designed for battery-backed applications. If a backup battery is not used, connect V CC to OUT, and connect BATT to ground.
Replacing the Backup Battery
The backup power source can be removed while VCC remains valid, without danger of triggering a reset pulse, if BATT is decoupled with a 0.1F capacitor to ground. As long as VCC stays above the reset threshold, battery-backup mode cannot be entered.
Using a SuperCapTM as a Backup Power Source
SuperCaps are capacitors with extremely high capacitance values (on the order of 0.47F) for their size. Since BATT has the same operating voltage range as VCC, and the battery switchover threshold voltages are typically 30mV centered at VBATT , a SuperCap and simple charging circuit can be used as a backup power source. Figure 11 shows a SuperCap used as a backup source. If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to OUT and VCC from BATT until the voltage at BATT is less than 0.5V above VCC. For example, if a SuperCap is connected to BATT through a diode to VCC, and VCC quickly changes from 5.4V to 4.9V, the capacitor discharges through OUT and VCC until VBATT reaches 5.1V typical. Leakage current through the SuperCap charging diode and the internal power diode eventually discharges the SuperCap to VCC. Also, if VCC and VBATT start from 0.1V above the reset threshold and power is lost at
Adding Hysteresis to the Power-Fail Comparator (MAX817/MAX819)
The power-fail comparator has a typical input hysteresis of 4mV. This is sufficient for most applications where a power-supply line is being monitored through an external voltage divider (see Monitoring an Additional Supply). For additional noise margin, connect a resistor between PFO and PFI, as shown in Figure 12. Select the ratio of R1 and R2 such that PFI sees VPFT when VIN falls to the
VIN R1 PFI R2 +5V
VCC
MAX817 MAX819
R3 C1* PFO
+5V VCC OUT MAX817 MAX818 MAX819 RESET TO STATIC RAM
GND TO P +5V PFO 0V 0V VL VTRIP VIN VH *OPTIONAL
BATT
TO P
100k
0.1F GND
R2 VTRIP = 1.25V R1 + R2
(
) )
1.25
R2
VH = 1.25V
(
R2 || R3 R1 + R2 || R3
Figure 11. Using a SuperCapTM as a Backup Power Source with a +5V 10% Supply SuperCap is a trademark of Baknor Industries.
VL - 1.25 5 - 1.25 = + R1 R3
Figure 12. Adding Hysteresis to the Power-Fail Comparator 13
______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1A to ensure that the 25nA (max) PFI input leakage current does not shift the trip point. R3 should be larger than 200k to prevent it from loading down the PFO pin. Capacitor C1 adds additional noise rejection.
+5V R1 PFI R2 VCC
MAX817 MAX819
PFO
Monitoring an Additional Supply (MAX817/MAX819)
The MAX817/MAX819 P supervisors can monitor either positive or negative supplies using a resistor voltage divider to PFI. PFO can be used to generate an interrupt to the P or to trigger a reset (Figures 9 and 13).
+5V GND V-
Interfacing to Ps with Bidirectional Reset Pins
Ps with bidirectional reset pins, such as the Motorola 68HC11 series, can contend with the MAX817/MAX818/ MAX819 RESET output. If, for example, the RESET output is driven high and the P wants to pull it low, indeterminate logic levels may result. To correct this, connect a 4.7k resistor between the RESET output and the P reset I/O, as in Figure 14. Buffer the RESET output to other system components.
PFO 0V VTRIP 0V
V5 - 1.25 1.25 - VTRIP = R1 R2 NOTE: VTRIP IS NEGATIVE
Figure 13. Monitoring a Negative Voltage
Negative-Going VCC Transients
These supervisors are relatively immune to short-duration, negative-going VCC transients (glitches) while issuing a reset to the P during power-up, power-down, and brownout conditions. Therefore, resetting the P when VCC experiences only small glitches is usually not desirable. The Typical Operating Characteristics show a graph of Maximum Transient Duration vs. Reset Threshold Overdrive for which reset pulses are not generated. The graph was produced using negative-going VCC pulses, starting at 3.3V and ending below the reset threshold by the magnitude indicated (reset threshold overdrive). The graph shows the maximum pulse width that a negativegoing VCC transient can typically have without triggering a reset pulse. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 135s will not trigger a reset pulse. A 0.1F bypass capacitor mounted close to the VCC pin provides additional transient immunity.
BUFFERED RESET TO OTHER SYSTEM COMPONENTS
VCC
VCC
MAX817 MAX818 MAX819
RESET
4.7k RESET
GND
GND
Figure 14. Interfacing to Ps with Bidirectional Reset I/O
14
______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
Watchdog Software Considerations (MAX817/MAX818)
To help the watchdog timer monitor software execution more closely, set and reset the watchdog input at different points in the program, rather than "pulsing" the watchdog input high-low-high or low-high-low. This technique avoids a "stuck" loop, in which the watchdog timer would continue to be reset within the loop, keeping the watchdog from timing out. Figure 15 shows an example of a flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should "hang" in any subroutine, the problem would quickly be corrected, since the I/O is continually set low and the watchdog timer is allowed to time out, triggering a reset or an interrupt. As described in the Watchdog Input Current section, this scheme results in higher average WDI input current than does the method of leaving WDI low for the majority of the timeout period and periodically pulsing it low-high-low.
MAX817L/M, MAX818L/M, MAX819L/M*
START
SET WDI LOW SUBROUTINE OR PROGRAM LOOP, SET WDI HIGH
RETURN
END
Figure 15. Watchdog Flow Diagram
__________Typical Operating Circuit
____Pin Configurations (continued)
TOP VIEW
+5V 0.1F CMOS RAM VCC BATT 0.1F
REALTIME CLOCK
OUT 1 VCC 2 GND 3
8
BATT RESET WDI CE OUT
MAX818
7 6 5
OUT CE IN 4 0.1F A0-A15 RESET P WDI** I/O ADDRESS DECODE OUT 1 VCC 2 GND 3 PFI 4 8 BATT RESET MR PFO
MAX817 MAX818 MAX819
RESET
DIP/SO/MAX
CE IN*
CE OUT* GND
MAX819
7 6 5
*CE IN AND CE OUT APPLY TO MAX818 ONLY. **WDI APPLIES TO MAX817/MAX818 ONLY.
DIP/SO/MAX
______________________________________________________________________________________
15
+5V Microprocessor Supervisory Circuits MAX817L/M, MAX818L/M, MAX819L/M*
Ordering Information (continued)
PART MAX817_EPA MAX817_ESA MAX818_CPA MAX818_CSA MAX818_CUA MAX818_EPA MAX818_ESA MAX819_CPA MAX819_CSA MAX819_CUA MAX819_EPA MAX819_ESA TEMP. RANGE -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C PIN-PACKAGE 8 Plastic DIP 8 SO 8 Plastic DIP 8 SO 8 MAX 8 Plastic DIP 8 SO 8 Plastic DIP 8 SO 8 MAX 8 Plastic DIP 8 SO
Chip Information
TRANSISTOR COUNT: 719
These parts offer a choice of reset threshold voltage. From the
table below, select the suffix corresponding to the desired threshold and insert it into the blank to complete the part number. Devices are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. SUFFIX L M RESET THRESHOLD (V) 4.65 4.40
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
DIM
C A 0.101mm 0.004 in B A1 L
e
A A1 B C D E e H L
INCHES MAX MIN 0.044 0.036 0.008 0.004 0.014 0.010 0.007 0.005 0.120 0.116 0.120 0.116 0.0256 0.198 0.188 0.026 0.016 6 0
MILLIMETERS MIN MAX 0.91 1.11 0.10 0.20 0.25 0.36 0.13 0.18 2.95 3.05 2.95 3.05 0.65 4.78 5.03 0.41 0.66 0 6
21-0036D
E
H
8-PIN MAX MICROMAX SMALL-OUTLINE PACKAGE
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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